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november 2007 hyb25dc128800c[e/f] hyb25dc128160c[e/f] 128-mbit double-data-rate sdram ddr sdram internet data sheet rev. 1.12
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com data sheet hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram qag_techdoc_rev400 / 3.2 qag / 2006-08-01 2 03062006-jxuk-e7r1 hyb25dc128800c[e/f], hyb25dc128160c[e/f] revision history: 2007-11 , rev. 1.12 page subjects (major chan ges since last revision) all adapted internet version all update images previous revision: 2007-10, rev 1.11 all update ballsize previous revision: 2007-01, rev 1.10 all quimonda update previous revision: 2005-07, rev 1.00 data sheet rev. 1.12, 2007-11 3 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram 1overview this chapter lists all main features of the product fa mily hyb25dc128[800/160]c[e/f] and the ordering information. 1.1 features ? double data rate architecture: tw o data transfers per clock cycle ? bidirectional data strobe (dqs) is transmitted and received with data, to be used in capturing data at the receiver ? dqs is edge-aligned with data for reads and is center-aligned with data for writes ? differential clock inputs ? four internal banks for concurrent operation ? data mask (dm) for write data ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? burst lengths: 2, 4, or 8 ? cas latency: 2, 2.5, 3 ? auto precharge option for each burst access ? auto refresh and self refresh modes ? ras-lockout supported t rap = t rcd ? 15.6 s maximum average periodic refresh interval ? 2.5 v (sstl_2 compatible) i/o ? v ddq = 2.5 v 0.2 v ? v dd = 2.5 v 0.2 v ? pg-tfbga-60 package with 3 depopulated rows (8 12 mm 2 ) ? pg-tsopii-66 package ? lead- and halogene-free = green product table 1 performance the 128-mbit double-data-rate sdram is a high-speed cmos, dynamic random-access memory containing 134,217,728 bits. it is internally co nfigured as a quad-bank dram. the 128-mbit double-data-rate sdram uses a double-data-rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the 128-mbit double-data-rate sdram effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal dra m core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the i/o pins. part number speed code ?5 ?6 unit speed grade component ddr400b ddr333 ? max. clock frequency @cl3 f ck3 200 166 mhz @cl2.5 f ck2.5 166 166 mhz @cl2 f ck2 133 133 mhz data sheet rev. 1.12, 2007-11 4 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capt ure at the receiver. dqs is a strobe transmitted by the during reads and by the memory co ntroller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. the 128-mbit double-data-rate sdram operates from a differential clock (ck and ck ; the crossing of ck going high and ck going low is referred to as the positive edge of ck). co mmands (address and control signal s) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is refe renced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sdram are burst oriented ; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the addr ess bits registered coincident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. the ddr sdram provides for programmable read or write burst le ngths of 2, 4 or 8 locations. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at t he end of the burst access. as with standard sdrams, the pipelined, multibank architecture of ddr sdrams al lows for concurrent operation, thereby providing high effective bandwidth by hi ding row precharge and activation time. an auto refresh mode is provided along with a power-saving power-down mode. all in puts are compatible with the industry standard for sstl_2. all outputs are sstl_2, class ii compatible. note: the functionality described and the timi ng specifications included in this dat a sheet are for the dll enabled mode of operation. table 2 order information for rohs compliant products part number 1) 1) hyb: designator for memory components 25dc: s at v ddq = 2.5 v 128: 128-mbit density 800/160: product variations 8 and 16 c: die revision c f/e: package type tsop and fbga l: low power version (available on request) - t hese components are specifically selected for low i dd6 self refresh currents -5, - 6: speed grade org. cas-rcd-rp latencies clock (mhz) cas-rcd-rp latencies clock (mhz) speed package note hyb25dc128800ce-5 8 3-3-3 200 2.5-3-3 166 ddr400b pg-tsopii-66 2) 2) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament an d of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. hyb25dc128160ce-5 16 HYB25DC128160CF-5 16 pg-tfbga-60 hyb25dc128800ce?6 8 2.5-3-3 166 2-3-3 133 ddr333b pg-tsopii-66 hyb25dc128160ce?6 16 hyb25dc128800cf?6 8 pg-tfbga-60 hyb25dc128160cf?6 16 data sheet rev. 1.12, 2007-11 5 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram 2 pin configuration the pin configuration of a ddr sdram is listed by function in table 3 (60 pins). the abbreviations used in the pin#/buffer# column are explained in table 4 and table 5 respectively. the pin numbering for fbga is depicted in figure 1 and that of the tsop package in figure 2 . table 3 pin configuration of ddr sdram ball#/pin# name pin type buffer type function clock signals g2, 45 ck i sstl clock signal note: ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). g3, 46 ck i sstl complementary clock signal h3, 44 cke i sstl clock enable: cke high activates, and cke low deactivates, internal clock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck and cke are disabled during power-down. input buffers, excluding cke, are disabled during self refresh. cke is an sstl_2 input, but will detect an lvcmos low level after v dd is applied on first power up. after v ref has become stable during the power on and initialization sequence, it must be mantained for proper operation of the cke receiver. for proper self- refresh entry and exit, v ref must be mantained to this input. control signals h7, 23 ras i sstl row address strobe g8, 22 cas i sstl column address strobe g7, 21 we i sstl write enable h8, 24 cs i sstl chip select note: all commands are masked when cs is registered high. cs provides for external bank se lection on systems with multiple banks. cs is considered part of the command code. the standard pinout includes one cs pin. address signals j8, 26 ba0 i sstl bank address bus 2:0 note: ba0 and ba1 define to which bank an active, read, write or precharge command is being applied. ba0 and ba1 also determines if the mode register or extended mode register is to be accessed during a mrs or emrs cycle. j7, 27 ba1 i sstl data sheet rev. 1.12, 2007-11 6 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram k7, 29 a0 i sstl address bus 11:0 l8, 30 a1 i sstl l7, 31 a2 i sstl m8, 32 a3 i sstl m2, 35 a4 i sstl l3, 36 a5 i sstl l2, 37 a6 i sstl k3, 38 a7 i sstl k2, 39 a8 i sstl j3, 40 a9 i sstl k8, 28 a10 i sstl ap i sstl j2, 41 a11 i sstl h2, 42 a12 i sstl address signal 12 note: 256 mbit or larger dies nc nc ? note: 128 mbit or smaller dies f9, 17 a13 i sstl address signal 13 note: 1 gbit based dies nc nc ? note: 512 mbit or smaller dies data signals 8 organization a8, 2 dq0 i/o sstl data signal 7:0 b7, 5 dq1 i/o sstl c7, 8 dq2 i/o sstl d7, 11 dq3 i/o sstl d3, 56 dq4 i/o sstl c3, 59 dq5 i/o sstl data signal b3, 62 dq6 i/o sstl a2, 65 dq7 i/o sstl data strobe 8 organisation e3, 51 dqs i/o sstl data strobe data mask 8 organization f3, 47 dm i sstl data mask ball#/pin# name pin type buffer type function data sheet rev. 1.12, 2007-11 7 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram data signals 16 organization a8, 2 dq0 i/o sstl data signal 15:0 b9, 4 dq1 i/o sstl b7, 5 dq2 i/o sstl c9, 7 dq3 i/o sstl c7, 8 dq4 i/o sstl d9, 10 dq5 i/o sstl d7, 11 dq6 i/o sstl e9, 13 dq7 i/o sstl e1, 54 dq8 i/o sstl d3, 56 dq9 i/o sstl d1, 57 dq10 i/o sstl c3, 59 dq11 i/o sstl c1, 60 dq12 i/o sstl b3, 62 dq13 i/o sstl b1, 63 dq14 i/o sstl a2, 65 dq15 i/o sstl data strobe 16 organization e3, 51 udqs i/o sstl data strobe upper byte e7, 16 ldqs i/o sstl data strobe lower byte data mask 16 organization f3, 47 udm i sstl data mask upper byte f7, 20 ldm i sstl data mask lower byte power supplies f1, 49 v ref ai ? i/o reference voltage a9, b2, c8, d2, e8, 3, 9, 15, 55, 61 v ddq pwr ? i/o driver power supply a7, f8, m7, 1, 18, 33 v dd pwr ? power supply a1, b8, c2, d8, e2, 6, 12, 52, 58, 64 v ssq pwr ? power supply a3,f2, m3, 34, 48, 66, v ss pwr ? power supply not connected a2, 65 nc nc ? not connected note: 4 organization a8, 2 nc nc ? not connected note: 4 organization b1, 63 nc nc ? not connected note: 8 and 4 organisation ball#/pin# name pin type buffer type function data sheet rev. 1.12, 2007-11 8 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram table 4 abbreviations for pin type b9, 4 nc nc ? not connected note: 8 and 4 organization c1, 60 nc nc ? not connected note: 8 and 4 organization c3, 59 nc nc ? not connected note: 4 organization c7, 8 nc nc ? not connected note: 4 organization c9, 7 nc nc ? not connected note: 8 and 4 organization d1, 57 nc nc ? not connected note: 8 and 4 organization d9, 10 nc nc ? not connected note: 8 and 4 organization e1, 54 nc nc ? not connected note: 8 and 4 organization e7, 16 nc nc ? not connected note: 8 and 4 organization e9, 13 nc nc ? not connected note: 8 and 4 organization f7, 20 nc nc ? not connected note: 8 and 4 organization f9, 14, 17, 19, 25,43, 50, 53 nc nc ? not connected note: 16, 8 and 4 organization abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectio nal input/output signal. ai input. analog levels. pwr power gnd ground nc not connected ball#/pin# name pin type buffer type function data sheet rev. 1.12, 2007-11 9 03062006-jxuk-e7r1 hyb25dc128[800/160]c[e/f] 128-mbit double-data-rate sdram table 5 abbreviations for buffer type figure 1 pin configuration pg-tfbga-60 top vi ew, see the balls through the package abbreviation description sstl serial stub terminated logic (sstl2) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 operat ional states, active low and tristate, and allows multiple devices to share as a wire-or. 0 3 3 + ' 0 8 $ 9 6 6 4 % $ 9 6 6 ' 4 8 ' 4 / ' 4 8 9 ' ' 4 ' 4 8 9 6 6 4 9 5 ( ) ' 4 9 6 6 9 6 6 4 $ ' / 4 $ 9 6 6 $ 9 ' ' $ % & ' ) * + - ( / 0 . 1 9 ' ' 4 2 ' 7 % $ % $ 9 6 6 9 ' ' 4 $ % $ 9 5 ( ) & |